1. Field of the Invention
The present disclosure generally relates to the fabrication of integrated circuits, and, more particularly, to various methods of performing gate cut etch processes for FinFET semiconductor devices.
2. Description of the Related Art
In modern integrated circuits, such as microprocessors, storage devices and the like, a very large number of circuit elements, especially transistors, are provided on a restricted chip area. Transistors come in a variety of shapes and forms, e.g., planar transistors, FinFET transistors, nanowire devices, etc. The transistors are typically either NMOS (NFET) or PMOS (PFET) type devices wherein the “N” and “P” designation is based upon the type of dopants used to create the source/drain regions of the devices. So-called CMOS (Complementary Metal Oxide Semiconductor) technology or products refers to integrated circuit products that are manufactured using both NMOS and PMOS transistor devices. Irrespective of the physical configuration of the transistor device, each device comprises drain and source regions and a gate electrode structure positioned above and between the source/drain regions. Upon application of an appropriate control voltage to the gate electrode, a conductive channel region forms between the drain region and the source region.
In some applications, fins for FinFET devices are formed such that the fin is vertically spaced apart from and above the substrate with an isolation material positioned between the fin and the substrate. FIG. 1A is a perspective view of an illustrative prior art FinFET semiconductor device 100 that is formed above a semiconductor substrate 105 at an intermediate point during fabrication. In this example, the FinFET device 100 includes three illustrative fins 110, an isolation material 130 (e.g., silicon dioxide, a low-k material or an ultra-low-k material), a gate structure 115, sidewall spacers 120 (e.g., silicon nitride) and a gate cap layer 125 (e.g., silicon nitride). The fins 110 have a three-dimensional configuration: a height, a width, and an axial length. The portions of the fins 110 covered by the gate structure 115 are the channel regions of the FinFET device 100, while the portions of the fins 110 positioned laterally outside of the spacers 120 are part of the source/drain regions of the device 100. Although not depicted, the portions of the fins 110 in the source/drain regions may have additional epi semiconductor material formed thereon in either a merged or unmerged condition.
Typically, fins are formed in a regular array. To define separate transistor devices, the length of the fins may be adjusted and some fins or portions of fins may be removed. For example, a fin cut or “FC cut” process cuts fins in the cross direction. Typically, an array of gate structures is formed above the remaining fin portion after the FC process. Subsequently a gate cut or “CT cut” process is performed to cut the gate structures in the cross direction. Each cut process requires a separate multilayer patterning stack and lithography processes, complicating the process flow and increasing the fabrication time of the semiconductor devices.
FIG. 1B illustrates cross-section views of the product 100 at a previous point in the process flow to illustrate a CT cut process. A placeholder gate structure 135 (e.g., a silicon dioxide gate dielectric layer and an amorphous silicon sacrificial material) was formed above the fins 110. A dielectric layer 140 was formed above the placeholder gate structure 135 and planarized to expose the placeholder gate structure 135. A replacement gate technique is employed at a later stage in the process flow to replace the placeholder gate structure 135 with a metal gate structure to allow work function tailoring. A hard mask layer 145 (e.g., silicon nitride) was formed above the dielectric layer 140, and a patterning layer 150 was formed above the hard mask layer 145. The patterning layer 150 may include a stack of layers such as a spin-on hard mask (SOH) layer, an oxide layer, a bottom anti-reflective coating (BARC) layer, a photoresist layer, etc. (not separately illustrated) that were patterned to define an opening 155 above the hard mask layer 145. In general, the opening 155 is a CT opening used to cut the gate structure 135.
FIG. 1C illustrates the product 100 after an etch process was performed in the presence of the patterning layer 150 to define a corresponding opening in the hard mask layer 145. Since the spacers 120 and the hard mask layer 145 may be both formed of silicon nitride, the etch process may erode the spacers 120. Also, since nitride-oxide selectivity is imperfect, especially for small features, portions of the dielectric layer 140 may also be eroded.
FIG. 1D illustrates the product 100 after a plurality of processes was performed to remove the patterning layer 150, remove the exposed portions of the placeholder gate structures 135, remove the hard mask layer 145, and fill the resulting recesses with an insulating material 160 (e.g., silicon nitride) to complete the CT process.
At later stages in the process flow, the remaining placeholder gate structures 135 are replaced and a self-aligned contact (SAC) etch process may be employed to define contacts between the replacement gate structures (not shown). The erosion of the spacers 120 and the dielectric layer 140 reduces the margin for the SAC process and increase the likelihood of a contact-to-contact short in the tip-to-tip region where the CT process was performed.
The present disclosure is directed to various methods and resulting devices that may avoid, or at least reduce, the effects of one or more of the problems identified above.